rev.1.0, sep.19.2003, page 1 of 9 M62383FP 5 v composite type d-a converter rej03f0076-0100z rev.1.0 sep.19.2003 description the M62383FP is a 5 v composite d-a converter incorporating two modules, with two 8-bit buffer amp output d-a converters and an 8-bit d-a converter for reference voltage adjustment as one module. the d-a outputs can be set simultaneously for each module without address setting. the data configurations comprise 16-bit serial data for the two main d-a circuits and 8-bit serial data for the reference voltage setting d-a. the d-a output buffer amps have full-swing output capability, from power supply voltage to gnd. features ? simultaneous dual-output data setting by means of 16-bit serial data (ttl level) ? data transfer clock frequency: 10 mhz (max.) ? d-a converter output settling time: 5 s (typ.) ? power-on reset and external reset (l reset) functions (d-a output = 0 v, mon output = vref 255/256) application automatic adjustment of electronic devices recommended operating conditions power supply voltage: 5 v 10% pin connection diagram (top view) mon x mon y d/a xx d/a yy d/a yx v cc d/a xy gnd gnd v refx v refy sdi refx sdi refy sld refx sck refy sck x sdi x sld y sdi y sck refx sld refy sld x sck y reset 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 M62383FP package: 24p2q-a
M62383FP rev.1.0, sep.19.2003, page 2 of 9 block diagram 5 23 24 22 20 21 19 6 1 7 17 18 16 14 15 13 9 8 10 11 12 4 3 2 mon x mon y d-a xx d-a yy d-a yx v cc d-a xy gnd gnd v refx v refy sdi refx sdi refy sld refx sck refy sck x sdi x sld y sdi y sck refx sld refy sld x sck y reset 8-bit shift register 16-bit shift register 8-bit d-a 8-bit d-a 8-bit d-a module 1 module 2 reset 8-bit latch 8-bit latch 8-bit latch
M62383FP rev.1.0, sep.19.2003, page 3 of 9 pin description pin no. symbol function 1, 11 gnd ground (gnd) pin 2 monx module 1: reference voltage d-a output pin 10 mony module 2: reference voltage d-a output pin 3 d/axx module 1: 8-bit d-a output pin (x side) 4 d/axy module 1: 8-bit d-a output pin (y side) 8 d/ayx module 2: 8-bit d-a output pin (x side) 9 d/ayy module 2: 8-bit d-a output pin (y side) 5 vrefx module 1: reference voltage input pin 7 vrefy module 2: reference voltage input pin 6 vcc power supply (vcc) pin 12 reset reset pin when input level is changed from ? h ? to ? l ? , d-a output becomes 0 v (d- a data: 00h), and mon output becomes vref 255/256 (mon data: ffh). even if input level is restored from ? l ? to ? h ? , output is maintained until next data setting. ttl-based. 19 sldx module 1: load signal input pin 13 sldy module 2: load signal input pin at rising edge of input signal from ? l ? to ? h ? , data in 16-bit shift register is loaded into d/a data register. ttl-based. 22 sldrefx module 1: reference voltage load signal input pin 16 sldrefy module 2: reference voltage load signal input pin at rising edge of input signal from ? l ? to ? h ? , data in 8-bit shift register is loaded into d/a data register. ttl-based. 20 sdix module 1: serial data input pin 14 sdiy module 2: serial data input pin ttl-based 16-bit-length serial data 23 sdirefx module 1: reference voltage serial data input pin 17 sdirefy module 2: reference voltage serial data input pin ttl-based 8-bit-length serial data 21 sckx module 1: shift clock signal input pin 15 scky module 2: shift clock signal input pin tll schmitt trigger based serial clock input sdi serial data is sent to 16-bit shift register one bit at a time at each rise. 18 sckrefx module 1: reference voltage shift clock signal input pin 24 sckrefy module 2: reference voltage shift clock signal input pin tll schmitt trigger based serial clock input sdiref serial data is sent to 8-bit shift register one bit at a time at each rise. absolute maximum ratings (unless specified otherwise, ta = 25 o c) item symbol rated value unit conditions power supply voltage vcc -0.3 to 7.0 v digital input voltage vdin -0.3 to vcc+0.3 ( 7.0) v dc voltage ( ? h ? level voltage) reference voltage input voltage vref -0.3 to vcc+0.3 ( 7.0) v output voltage vdaout -0.3 to vcc+0.3 ( 7.0) v internal permissible loss pd 500 mw operating ambient temperature topr -20 to +85 c storage temperature tstg -55 to +150 c
M62383FP rev.1.0, sep.19.2003, page 4 of 9 recommended operating conditions (unless specified otherwise, vcc = 5 v 10%, vref = vcc, fsck = 5 mhz, vih = vcc, vil = gnd, ta = 25 o c) specification values item symbol min. typ. max. unit test conditions power supply voltage vcc 4.5 5.0 5.5 v reference power supply voltage vref gnd vcc v vcc voltage or below clock frequency fsck 10 mhz ?h? level input voltage vih 2 vcc v ttl ?h? input level ?l? level input voltage vil gnd 0.8 v ttl ?l? input level clock input hysteresis voltage v ? 0.4 0.6 1.0 v ttl schmitt trigger clock ?l? pulse width tsckl 30 450 ns see timing chart clock ?h? pulse width tsckh 30 450 ns see timing chart clock rise time tsckr 10 100 ns see timing chart clock fall time tsckf 10 100 ns see timing chart data setup time tdch 10 100 ns see timing chart data hold time tchd 20 200 ns see timing chart load setup time tchl 40 800 ns see timing chart load hold time tldc 20 400 ns see timing chart load ?h? pulse time tldh 20 400 ns see timing chart reset ?h? pulse time trstl 50 ns see timing chart timing chart t sckr t sckl t dch v oa = 0.5v, v or = 0.5v v oa = 4.5v, v or = 4.5v t chd t chl t rstl t ldh t ldc 0.5v 0.5lsb 0.5lsb t ldd t ldd t sckf t sckh sck sdi sld reset
M62383FP rev.1.0, sep.19.2003, page 5 of 9 electrical characteristics (unless specified otherwise, vcc = 5 v 10%, vref = vcc, fsck = 5 mhz, vih = vcc, vil = gnd, ta = -20 o c to 85 o c) (a) common to analog and digital blocks specification values item symbol min. typ. max. unit test conditions circuit current icc 6.0 10 ma (b) digital block specification values item symbol min. typ. max. unit test conditions input leakage current iilk ? 10 10 a vin = 0v to 5v
M62383FP rev.1.0, sep.19.2003, page 6 of 9 (c) analog block specification values item symbol min. typ. max. unit test conditions reference voltage input voltage vref gnd vcc v when sdiref is set to (ff)h, vref = mon reference voltage input current iref ? 1 +1 a gnd vref vcc upper reference voltage output voltage (*1) voru 4.88 4.98 vcc v sdiref = (ff)h, sdi = (ffff)h, mon output value lower reference voltage output voltage (*1) vorl gnd 0.10 v sdiref = (00)h, sdi = (ffff)h, mon output value reference voltage output offset voltage (*1) ? vor ? 100 100 mv vref = 2 to 5v, sdi = (ffff)h, 255/256vref-vor (mon output value) upper buffer amp d-a output voltage voau 4.5 v ioa = 0.5ma, sdiref = (ff)h, sdi = (ffff)h lower buffer amp d-a output voltage voal 0.05 v ioa = 0.5ma, sdiref = (ff)h, sdi = (0000)h accuracy: differential nonlinearity error sdl ? 1.0 +1.0 lsb (monotone increasing capability) accuracy: nonlinearity error snl ? 1.0 +1.0 lsb accuracy: zero scale error szero ? 2.0 +2.0 lsb vref = 2 to 5 v: buffer output offset (*2) accuracy: full-scale error sfull ? 2.0 +2.0 lsb vref = 2 to 5 v: buffer output offset (*2) reference voltage input pin capacitance cref 10 pf d-a converter output settling time tldda 5 10 s voa = 0.5 ? 4.5v, ioa = 0.1ma, co = 50pf, sdiref = (ff)h, time for output to be absorbed within 0.5 lsb reference voltage output settling time tlddr 10 20 s voa = 0.5 ? 4.5v, no external load time for output to be absorbed within 0.5 lsb power-on reset voltage (*3) v reset 0.8 1.5 3 v vcc = 0 5v, voa = 0v, vor = vref 255/256 set notes: 1. mon output specification. equivalent to 5 lsb. 2. d-a output (d-axx, d-axy, d-ayx, d-ayy) specification. mon output is stipulated by 3 items in *1 above (voru, vorl, ? vor). 3. reference values
M62383FP rev.1.0, sep.19.2003, page 7 of 9 digital data format sck sdi msbn * d-a converter serial data is msb-first data. lsb sld d-a sdix, sdiy sdirefx, sdiref msb d 15 d 14 d 13 d 12 d 11 d 10 d 09 d 08 d 07 d 06 d 05 d 04 d 03 d 02 d 01 d 00 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7x d 6x d 5x d 4x d 3x d 2x d 1x d 0x d 7y d 6y d 5y d 4y d 3y d 2y d 1y d 0y lsb msb lsb v oa : d-a output voltage v or : mon output voltage dn * : d-a data n = 0 to 7, * = x, y v or : mon output voltage v ref : reference voltage 2 7 d 7 * +2 6 d 6 * +2 5 d 5 * +2 4 d 4 * +2 3 d 3 * +2 2 d 2 * +2 1 d 1 * +2 0 d 0 * 256 v oa = v or 2 7 d 7 +2 6 d 6 +2 5 d 5 +2 4 d 4 +2 3 d 3 +2 2 d 2 +2 1 d 1 +2 0 d 0 256 v oa = v ref usage notes 1. this ic has three pins to which a constant voltage is applied during use (constant-voltage input pins: vcc, vrefx, vrefy). if ripples or spikes are imposed on these pins, d-a conversion accuracy may fall. when using this ic, a capacitor (1 f or higher recommended) must be inserted between the constant-voltage input pins and ground (gnd) in order to ensure stable d-a conversion. 2. with regard to the reset function (power-on reset), when the power supply voltage passes the vicinity of 1.5 v at power-on, the d-a output voltage (voa) becomes 0 v (d-a data: 00h), and the mon output voltage (vor) becomes vref 255/256 (mon data: ffh), and output is maintained until the next data is set. in the event of repeated power supply on/off operations at short intervals, a reset may not be effected because of the simplicity of the circuit.
M62383FP rev.1.0, sep.19.2003, page 8 of 9 sample standard application circuit M62383FP 5v module 1 d-a data module 2 d-a data d-ax* reference voltage monitoring d-a output d-a output d-ay* reference voltage monitoring h: fixed 1 2 3 4 5 6 7 8 9 10 11 12 15 14 13 18 17 16 20 19 23 24 22 21 xx xy yx yy
M62383FP rev.1.0, sep.19.2003, page 9 of 9 package dimensions ssop24-p-300-0.80 weight(g) ? jedec code 0.2 eiaj package code lead material cu alloy 24p2q-a plastic 24pin 300mil ssop symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h e a 1 i 2 ? ? .3 0 0 .18 0 .0 10 .2 5 ? .5 7 .4 0 ? ? ? .27 1 .1 0 ? .8 1 .35 0 .2 0 .1 10 .3 5 .8 0 .8 7 .6 0 .25 1 ? .62 7 ? .2 0 .1 2 ? .45 0 .25 0 .2 10 .4 5 ? .1 8 .8 0 ? .1 0 ? b 2 ? ? 5 0. ? 0 ? 8 e e 1 24 13 12 1 h e e d e y f a a 2 a 1 l 1 l c e b 2 e 1 i 2 recommended mount pad detail f ? ? z 1 0.65 ? ? 0.8 z detail g z z 1 b g mmp
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